1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an electrically erasable nonvolatile semiconductor device.
2. Description of the Prior Art
There have been proposed various electrical methods to erase data written in a nonvolatile semiconductor read-only memory.
For example, data can be electrically restored in the EEPROM (electrically erasable programmable read-only memory) by using electrons which pass through a thin insulating layer due to the tunneling effect.
However, since the EEROM requires two MOS transistors form a single memory cell, the EEPROM is inferior in its density of integration with respect to an EPROM (erasable programmable read-only memory) in which stored data can be erased by ultraviolet light. Moreover, the EEPROM requires a high voltage on the order of 21 volts for enabling the tunneling effect, which requires a complex power circuit. To eliminate such a disadvantage, there have been proposed EEPROMs with a high density of integration employing MOS memory elements each having a floating gate as shown in FIG. 3, employed in the conventional EPROM.
Such EEPROMs are disclosed, for example, in Japanese Patent Publication Nos. 61-6475, 61-20958, 61-30351 and 61-30354, Japanese Laid-Open Patent Publication No. 61-165895, and IEEE International Solid-State Circuit Conference, Digest of Technical Papers pp. 76-77, 345 (Feb. 25, 1987).
A writing operation of the EEPROM, in a fashion similar to that of the conventional EPROM, is implemented by injecting hot electrons generated in the vicinity of the drain region into the floating gate.
The following two methods have been proposed for an erasing operation.
In the first method, a high voltage is applied to the drain region 3 of a MOS memory element as shown in FIG. 3 and the source region 4 and the control gate electrode 1 are connected to a ground to reduce the potential of a floating gate sufficiently. Consequently, electrons move from the floating gate to the electrode of a higher potential due to the tunneling effect, whereby data stored in the MOS memory element is erased. In this method, however, it is difficult to control the potential of the floating gate of the MOS memory element after the erasing operation.
A second method uses the breakdown effect at the drain region of a MOS memory element employed in the EPROM. In the erasing operation, a high voltage, a ground voltage and a negative voltage are applied respectively to the drain region 3, a p-type substrate and a control gate 1 of a MOS memory element to induce breakdown in the vicinity of the drain region. Consequently, holes having high energy are injected into the floating gate to erase data stored in the MOS memory element. However, the erasing operation requires a high current and a negative voltage which must be applied to the control gate of the MOS memory element. Since the source region and drain region of an n-type transistor cannot be biased by a negative voltage, it is necessary that a negative voltage applying means for the control gate be formed of a PMOS transistor formed in the n-type well and a load resistance of polycrystalline silicon, which requires a complex circuit construction.
These erasing methods are not applicable to E/D (enhancement/depletion) MOS EPROM ICs, which are currently the most popular type of ICs.